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Espressif Systems /ESP32-S3 /SENSITIVE /CORE_0_DRAM0_PMS_MONITOR_2

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Interpret as CORE_0_DRAM0_PMS_MONITOR_2

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR)CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR 0 (CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK)CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK 0CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR

Description

core0 dram0 permission monitor configuration register 2.

Fields

CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR

recorded core0 dram0 permission monitor interrupt status.
CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK

recorded core0 dram0 lock status, 1 means s32c1i access.
CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD

recorded core0 dram0 world status, 0x1 means world0, 0x2 means world1.
CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR

recorded core0 dram0 address[25:4] status when core0 dram0 violated permission,the real address is 0x3c000000+addr*16

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data